In the manufacture of an integrated circuit device bond pads are created on the device to receive circuit connectors that provide external electrical connection to the metal layers of the integrated circuit device. The methods that are used in the prior art to create a bond pad opening in the device typically etch through the various layers of the integrated circuit device. The uppermost layer is usually a passivation layer. Under the passivation layer is an anti-reflective coating layer (sometimes referred to as an ARC layer) that comprises the top layer of a metal stack. The remainder of the metal stack is located under the ARC layer. The metal stack is typically located on an underlying oxide layer.
Prior art methods mask and etch a bond pad opening through the passivation layer and through the ARC layer down to the metal stack. This method leaves the interior edges of the ARC layer exposed to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device. The interior edges of the ARC layer corrode rapidly when exposed to the high temperatures and high humidity that are present during subsequent accelerated reliability testing procedures. In addition, corrosion can occur in the assembly process from the exposure to corrosive materials used in die packaging. The corrosion of the exposed interior edges of the ARC layer can extend for hundreds of microns through the ARC layer. Corrosion in the ARC layer leads to device failure by creating high electrical resistance and cracks in the overlying passivation layer.
To better illustrate the problem FIG. 1 shows a schematic diagram of a plan view of a prior art bond pad structure 100. The top layer shown in FIG. 1 is the anti-reflective coating layer 110 (ARC layer 110). FIG. 2 shows a schematic diagram 200 of a cross sectional view of the bond pad structure 110 taken along the line A-A in FIG. 1. As shown in FIG. 2, the top layer is ARC layer 110. The ARC layer 110 is typically formed of titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium tungsten (TiW), or other metals.
The bottom layer shown in FIG. 2 is an oxide layer 210 that is located on a substrate (not shown). Metal stack 220 is located on oxide layer 210. Metal stack 220 may typically comprise metals such as aluminum (Al), copper (Cu), titanium (Ti), titanium nitride (TiN), and other metals. The ARC layer 110 is located on the metal stack 220. The thicknesses of the various layers of the prior art bond pad structure shown in FIG. 2 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 2 are shown larger than actual size.
The bond pad structure 100 is subsequently covered with a passivation layer 310. A mask and etch process is performed to etch a bond pad opening 320 through the passivation layer 310 and through the ARC layer 110 down to the metal stack 220. FIG. 3 shows a schematic diagram 300 of a plan view of the prior art bond pad structure 100 covered with passivation layer 310. The top layer shown in FIG. 3 is the passivation layer 310 that is located over the ARC layer 110. The metal stack 220 (not numbered in FIG. 3) is visible through the bond pad opening 320.
FIG. 4 shows a schematic diagram 400 of a cross sectional view of the bond pad structure shown in FIG. 3 taken along the line B-B in FIG. 3. As shown in FIG. 4, the etch process that creates bond pad opening 320 exposes the interior edges 410 of the ARC layer 110 to the ambient atmosphere. As previously described, the interior edges 410 of the ARC layer 110 are subject to corrosion during their exposure to high temperature, high humidity and corrosive materials during the subsequent assembly operations of the integrated circuit device.
The thicknesses of the various layers of prior art bond pad structure shown in FIG. 4 are not necessarily drawn to scale. For clarity the thicknesses of the various layers in FIG. 4 are shown larger than actual size.
FIG. 5 illustrates a flowchart 500 showing the steps of the prior art method and how the prior art method exposes the interior edges 410 of the ARC layer 110 to corrosion. First, an oxide layer 210 is deposited on a substrate (not shown) (step 510). Then a metal stack 220 is deposited on the oxide layer 210 (step 520). Then an anti-reflective coating layer 110 (ARC layer 110) is deposited on the metal layer 220 (step 530).
Then a passivation layer 310 is deposited on the ARC layer 110 (step 540). Then a mask and etch process is performed on the passivation layer 310 to etch the bond pad opening 320 through the passivation layer 310 and through the anti-reflective coating layer 110 (ARC layer 110) down to the metal stack 220. The mask and etch process exposes the interior edge portions 410 of the ARC layer 110 in the bond pad opening 320. The interior edge portions 410 of the ARC layer 110 become corroded due to exposure to the ambient atmosphere during the subsequent assembly operations of the integrated circuit device (step 560).
Therefore, there is a need in the art for a system and method that is capable of solving the above described corrosion problem that occurs in ARC layers of prior art bond pad structures.
The present invention provides a system and method that seals the interior edges of the ARC layer so that the interior edges of the ARC layer are not subject to corrosion. An ARC layer removal mask and etch step is inserted between a metal pad define step and a subsequent passivation deposition step. During the ARC layer removal mask and etch step a central portion of the ARC layer is removed from a central portion of the bond pad.
Normal processing is resumed after the ARC layer removal mask and etch step. A passivation deposition step is performed. Then a mask and etch process is performed to etch the bond pad opening through the passivation layer. A design rule of the present invention ensures that the interior edges of the etched passivation layer always overlap and cover the interior edges of the ARC layer.
Before undertaking the Detailed Description of the Invention below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like.
Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior uses, as well as to future uses, of such defined words and phrases.